NLIR1280ES High-Performance Uncooled Thermal Camera Modules

The 1280 uncooled thermal camera modules integrate a new-generation high-sensitivity vanadium oxide (VOx) infrared detector, delivering consistent high-performance core processing, ultimate imaging algorithms, and advanced lens control technology optimized for long-distance surveillance. Upgraded with next-generation imaging algorithms and paired with a 1280×1024 large-format sensor, this thermal imaging core is heavily optimized for challenging environmental conditions such as forests, sea surfaces, skies, rain, and fog, providing sharper and clearer infrared images.

To satisfy the demands of comprehensive infrastructure development, the module supports athermal fixed lenses, fixed-focus electric lenses, and continuous zoom lenses, enabling electric focusing, continuous zooming, auto-focusing, and defocus compensation. The architecture offers versatile video output interfaces including Ethernet, LVCMOS, BT.1120, and MIPI, with extensible hardware interfaces such as SDI, USB, CameraLink, and HDMI. An easy-to-use SDK is provided to shorten R&D cycles, improve efficiency, and reduce secondary development costs for integrators.

As one of the most reliable uncooled thermal camera modules available, the NLIR1280ES is widely deployed across demanding sectors requiring persistent observation:

• Perimeter Security: Establishes tight virtual fences and intelligent thermal tripwires.
• High-Altitude Observation: Mounted on elevated platforms for macro thermal analytics.
• Forest Fire Prevention: Continuously scans forestry to detect early-stage fire signatures.
• Water Area Monitoring: Pierces through maritime environments for vessel tracking.
• Industrial Temperature Measurement & Railway Monitoring: Provides non-contact thermal tracking for critical infrastructure and transit lines.

The user extension component is designed for the 1280 uncooled infrared core module. It contains 5 sockets as shown in Figure 4.1, supporting power input, RS-485, Ethernet, alarm I/O, audio I/O, MIPI and other interfaces. Interface definitions are shown in the figures below.

LVCMOS includes 1 clock, 1 frame sync (Fsync), 1 line sync (Lsync), and 14 parallel data signal lines. When a frame of data arrives, the frame synchronization signal is set to high level, indicating that the following data belong to the same frame. When the frame ends, the frame synchronization signal is set to low level, indicating the end of the frame. Similarly, when a line of data arrives, the line synchronization signal is set to high level; when the line ends, the line synchronization signal is set to low level.

The timing diagram of LVCMOS video is shown in the figure below.

The LVCMOS video data source can be selected from original data (ORG), non-uniformity corrected data (NUC), image denoised data (DNS), and image processed data (DRC). Among these sources, DRC data is 8-bit per pixel, while all other sources are 14-bit per pixel. In the figure above, the synchronization signals and data signals change on the rising edge of the clock. In practical program design, signals can be set to change on the falling edge of the clock, so that the receiver can sample on the rising edge of the clock. Data sources: ORG, NUC, DNS (14-bit), DRC (8-bit).

For the BT.1120 digital video timing of the uncooled infrared core module, there are two modes: internal synchronization and external synchronization. Internal synchronization uses synchronization reference codes to indicate the start and end of each line or frame. It includes 16 data lines and 1 clock line. External synchronization includes 16 data lines, 1 clock line, plus one line synchronization signal and one field synchronization signal.

The default BT.1120 digital video source is DRC and cannot be modified. The BT.1120 video output by the uncooled infrared core module supports both internal and external synchronization modes. That is, the 16 data lines carry synchronization reference codes, while line sync and field sync signals are also output simultaneously. Data transitions on the falling edge of the clock to ensure stable sampling at the receiving end on the rising edge of the clock. The video resolution output by the 1280 core is 1280 columns × 1024 lines.

At line sync, 16-bit data outputs: high 8-bit chroma, low 8-bit luma. During blanking: outputs 0x8010.

The table above illustrates the format of a single frame of video. A frame consists of inactive rows and active rows, as well as blanking areas and active data areas. The top-left corner of the table corresponds to the start of the frame, and the bottom-right corner corresponds to the end of the frame. The specific frame size, the number of inactive/active rows, and the size of the blanking areas are determined by the actual configuration of the core module. All data in the blanking area is set to 0x8010. Each reference code occupies 4 clock cycles, and each pixel data occupies 1 clock cycle. Both the reference codes and pixel data are 16-bit. The format of the reference codes is shown in the table below:

In the internal synchronization mode, the 16-bit active pixel data is also structured as follows: the high 8 bits are chroma data, and the low 8 bits are luma (grayscale) data. Each reference code begins with three clock cycles of 0xFFFF, 0x0000, and 0x0000.

The CDS_2 video of the 1280 core is based on BT.1120 video with additional temperature data, enabling simultaneous output of image data and temperature data. In CDS_2 video, the output image is identical to BT.1120 video; however, the bit order within each pixel is reversed: In CDS_2, the high 8 bits are luminance (Y), and the low 8 bits are chrominance (CbCr). This is the opposite of the standard BT.1120 format.

The overall structure of CDS_2 video is very similar to BT.1120, with the only difference being that temperature data is embedded within the active data payload. CDS_2 video requires the following signals: 1 clock line (clk), 1 frame sync line (fsync), 1 line sync line (lsync), 16 parallel data lines. The signals use a 3.3V high level and 0V low level. When outputting temperature data, the two most significant bits (MSBs) of the 16-bit data bus are driven low. The DVP-interface CDS_2 video format is only supported for 1280@30Hz core modules.

The data format of one frame of CDS_2 video is shown in the table below:

The internal synchronization codes of CDS_2 video are identical to those of BT.1120 video. CDS_2 video also supports both internal and external synchronization modes. In addition to the clock and data signals, it includes line synchronization and frame synchronization signals. The high-level duration of the line sync signal in CDS_2 video is twice that of BT.1120 video. For the 16-bit image data, the high 8 bits represent luminance (Y), and the low 8 bits represent chrominance (CbCr). The timing format of a line containing active data in CDS_2 video is shown in the figure below:

The MIPI video format serializes parallel digital video data using the MIPI protocol. Depending on the selected original parallel digital video format, the 1280 core can output image data independently. The MIPI video of the 1280 core adopts the CSI-2 interface standard with D-PHY physical layer and 4-lane transmission, requiring 1 pair of high-speed differential clock signal lines and 4 pairs of high-speed differential data signal lines.

MIPI-CSI uses standard short packets for synchronization. Each frame consists of the vertical blanking area, frame start packet (FS), frame end packet (FE), line blanking area, and data long packets. A data long packet includes a packet header (PH), packet footer (PF), and an active data area. A simplified diagram of one frame of MIPI video output by the core is shown in the table below:

The frame synchronization short packets (FS/FE) of MIPI video include Data ID, Short Packet Data Field, and VCX + ECC. The header (PH) of a data long packet contains Data ID, Word Count, and VCX + ECC, while the footer (PF) is a checksum using the CCITT-standard CRC16 algorithm. Packets are connected via EOT-LPS-SOT. The frame synchronization short packet format is shown in Table 4.14 below, the packet header/footer format in Table 4.15, and the EOT and SOT formats in Table 4.16.

For the 1280 core, the default output data format is YUV422 8 ‑ bit, transmitted in UYVY order. The line timing is shown in Figure 4.6. The clock signal enters high ‑ speed mode at the start of each frame and exits high ‑ speed mode at the end of the frame. Between frames, the interface enters low ‑ power mode (both data and clock lines are held at 1.2V high level). The frame timing is shown in Figure 4.7:

Note: Dimensions of these uncooled thermal camera modules vary with different lenses and extension components.

• • To protect your uncooled thermal camera modules and others from injury and prevent equipment damage, please read all information before use.
  • Do not direct the thermal imager at intense radiation sources such as the sun.

• Recommended operating temperature: -20℃ to 50℃.
• Do not touch or bump the detector window with hands or foreign objects.
• Do not touch the device or cables with wet hands.
• Do not bend or damage cables.
• Do not clean the device with diluents.
• Do not plug/unplug cables while powered on.
• Avoid incorrect wiring to prevent damage.
• Protect against static electricity.
• Do not disassemble the device; contact the manufacturer for professional repair in case of failure.